1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, it is concerned with a semiconductor device having an element isolation structure and a method of manufacturing such a semiconductor device.
2. Description of the Background Art
In manufacturing semiconductor integrated circuitry, it is necessary to form an element isolation structure which isolates respective elements electrically for controlling individual elements completely independently in operation thereby avoiding an electrical interference among elements. Generally, a LOCOS (Local Oxidation of Silicon) method has widely been known to form the element isolation structure, and many revisions are made for that method for common use.
In the LOCOS method, in general, a channel stopper region is provided under an element isolation oxide film so as to improve an element isolation effect. The channel stopper region, however, is formed in contact with a bottom surface of the element isolation oxide film, i.e., in a position relatively shallow from a substrate surface. Also, a parasitic capacitance is generated in a p-n junction portion formed by the channel stopper region and the substrate. As a result, the parasitic capacitance generated in a position close to an element formed on the substrate surface. When, for example, a bipolar transistor is isolated by the element isolation oxide film formed by the LOCOS method, a high speed operation of the bipolar transistor is hindered by the parasitic capacitance.
Thus, a trench isolation is commonly used in the element isolation structure for isolating the bipolar transistor from the other elements. However, in the structure using only the trench for isolation, the parasitic capacitance tends to be generated between an Al (aluminum) interconnection to be formed in the subsequent step and the substrate. In this regard, a thick oxide film, for example, the element isolation oxide film formed by the LOCOS method, is required between the Al interconnection and the substrate.
As described above, a combination of the element isolation oxide film formed by the LOCOS method and the trench is adapted for the element isolation structure isolating the bipolar transistor from the other elements.
In the following, a conventional semiconductor device having an element isolation structure employed in a Bi-CMOS structure which includes a bipolar transistor and a CMOS (Complementary Metal Oxide Semiconductor) transistor on the same semiconductor substrate will be described.
FIG. 51 is a schematic sectional view of the Bi-CMOS structure in the conventional semiconductor device. Referring to FIG. 51, the Bi-CMOS structure includes on the same semiconductor substrate a bipolar transistor region 550, a pMOS transistor region 560, an nMOS transistor region 570, and an element isolation region 520.
Element isolation region 520 serves as a region for mainly isolating bipolar transistor region 550 from CMOS transistor regions 560, 570.
First, in bipolar transistor region 550, an n.sup.+ buried layer 523 is formed on the surface of a p.sup.- silicon substrate 521. On the surface of n buried layer 523, an n.sup.- epitaxial growth layer 525 and an n.sup.+ collector wall region 523a are formed.
A base region 551 and an n.sup.+ emitter region 553 are formed on the surface of n.sup.- epitaxial growth layer 525. n.sup.+ emitter region 553 is surrounded at its periphery by base region 551. Base region 551 is formed by a two-layered structure consisting of a p.sup.+ base region 551a and a p type base region 551b.
A conductive layer 535 for extracting a base electrode is formed in contact with the surface of base region 551. The surface of conductive layer 535 for extracting the base electrode is covered by an insulating layer 537. A conductive layer 539 for extracting an emitter electrode is formed in contact with the surface of n.sup.+ emitter region 553 via a contact hole 537f provided in insulating layer 537. Also, a conductive layer 543 is formed via a contact hole 541a provided in two insulating layers 537, 541 so as to be in contact with the surface of n.sup.+ collector wall region 523a.
Next, in pMOS transistor region 560, n.sup.+ buried layer 523 is formed on the surface of p.sup.- silicon substrate 521. n.sup.- epitaxial growth layer 525 is formed on the surface of n.sup.+ buried layer 523. A pMOS transistor is formed on the surface of n.sup.- epitaxial growth layer 525.
The pMOS transistor includes a gate oxide film 561, a gate electrode 563, and a pair of p.sup.+ source/drain regions 565, 565. Pair of p.sup.+ source/drain regions 565, 565 are formed spaced by a predetermined distance from each other on the surface of n.sup.- epitaxial growth layer 525. Gate electrode 563 is formed on a region sandwiched by the pair of p.sup.+ source/drain regions 565, 565 with gate oxide film 561 interposed therebetween.
Insulating layers 537, 541 are formed to cover the pMOS transistor. A contact hole 541b is formed penetrating through two insulating layers 537, 541 to reach a part of the surface of pair of p.sup.+ source/drain regions 565, 565. A conductive layer 569 is formed in contact with p.sup.+ source/drain regions 565, 565 via contact hole 541b.
In nMOS transistor region 570, a p.sup.+ buried layer 524 is formed on the surface of p.sup.- silicon substrate 521. p type region 527 is formed on the surface of p.sup.+ buried layer 524 by selectively implanting ions. The nMOS transistor is formed on the surface of p type region 527 made by selective ion implantation.
The nMOS transistor includes a gate oxide film 571, a gate electrode 573, and a pair of n.sup.+ source/drain regions 575, 575. The pair of n.sup.+ source/drain regions 575, 575 are formed spaced by a predetermined distance from each other on the surface of p type region 527 made by selective ion implantation. Gate electrode 573 is formed on a region sandwiched by the pair of n.sup.+ source/drain regions 575, 575 with gate oxide film 571 interposed therebetween.
Insulating layers 537, 541 are formed to cover the nMOS transistor. A contact hole 541c is formed penetrating through two insulating layers 537, 541 to reach a part of the surface of pair of n.sup.+ source/drain regions 575, 575. A conductive layer 579 is formed in contact with n.sup.+ source/drain regions 575, 575 via contact hole 541c.
In element isolation region 520, an element isolation oxide film 501b is formed on the surface of n.sup.- epitaxial growth layer 525. A through hole 507a reaching the surface of n.sup.- epitaxial growth layer 525 is formed in element isolation oxide film 501b. Under through hole 507a, a trench 507b penetrating through n.sup.- epitaxial growth layer 525 and n.sup.+ buried layer 523 to reach a position at a predetermined depth of p.sup.- silicon substrate 521.
A silicon oxide film 513 having a predetermined thickness is formed to cover the inner wall of trench 507b. A filling layer 517a is formed for filling trench 507b with the top surface thereof positioned within through hole 507a. Filling layer 517a is made of a polycrystalline silicon layer without any impurity implanted thereinto. A silicon oxide film 519 is formed on filling layer 517a.
A p.sup.+ channel stopper region 515 is formed in a region under trench 507b in p.sup.- silicon substrate 521.
Now, a method of manufacturing the conventional semiconductor device will be described below.
FIGS. 52-64 are schematic cross sectional views showing in this order the manufacturing method of the conventional semiconductor device. First referring to FIG. 52, n.sup.+ buried layer 523 and n.sup.- epitaxial growth layer 525 are formed stacked successively on the surface of p.sup.- silicon substrate 521. A silicon oxide film 501a is formed on the surface of n.sup.- epitaxial growth layer 525 by thermal oxidation. A silicon nitride film 502 which is patterned into a desired shape is formed on the surface of silicon oxide film 501a by a CVD (Chemical Vapor Deposition) method and the like. Using silicon nitride film 502 as a mask, thermal oxidation is selectively conducted.
Referring to FIG. 53, by this thermal oxidation, element isolation oxide film 501b is formed on the surface of n.sup.- epitaxial growth layer 525, and then, silicon nitride film 502 is removed.
Referring to FIG. 54, by removal of the silicon nitride film, surfaces of silicon oxide film 501a and element isolation oxide film 501b are exposed.
Referring to FIG. 55, a silicon nitride film 503 and a silicon oxide film 505 are formed stacked successively on the entire surface of the substrate by the CVD method.
Referring to FIG. 56, an opening 507c penetrating through silicon oxide film 505 and silicon nitride film 503 is formed by photolithography and an RIE (Reactive Ion Etching) method. A through hole 507a penetrating through element isolation oxide film 501b is formed at a portion where element isolation oxide film 501b is exposed from opening 507c. Then, anisotropic etching is carried out on the surface of n.sup.- epitaxial growth layer 525 exposed from through hole 507a. With thus etched, a trench 507b penetrating through two layers, that is, n.sup.- epitaxial growth layer 525 and n.sup.+ buried layer 523 to reach a predetermined depth of p.sup.- silicon substrate 521 is formed.
Referring to FIG. 57, a rough surface is generated on the internal wall of trench 507b due to etching at the time of formation of trench 507b. Thermal oxidation is initially conducted in order to remove such roughness. The internal wall of trench 507b is oxidized through the thermal oxidation processing to form a silicon oxide film 511 covering the internal wall of trench 507b. Then, wet etching is carried out to remove silicon oxide film 511, eliminating the roughness of internal wall of trench 507b.
Referring to FIG. 58, such wet etching causes removal of silicon oxide film 511 covering the internal wall of trench 507b, and at the same time, etching-away of element isolation oxide film 501b and silicon oxide film 505 to a certain extent. More specifically, element isolation oxide film 501b is etched-away in a lateral direction from the wall surface of through hole 507a, since etching is carried out isotropically in wet etching. Also, silicon oxide film 505 is etched-away isotropically from the surface thereof by a predetermined amount.
Referring to FIG. 59, thermal oxidation processing is carried out again. Thus, the internal wall of trench 507b is oxidized to form a silicon oxide film 513 covering the internal wall of trench 507b. Ions are implanted onto the entire surface of the substrate, so that p type ions are implanted into p.sup.- silicon substrate 521 under the bottom surface of trench 507b. p.sup.+ channel stopper region 515 is then formed by activating/diffusing the ions implanted into p.sup.- silicon substrate 521.
Referring to FIG. 60, a polycrystalline silicon film 517 without any impurity implanted thereinto is formed on the entire surface of silicon oxide film 505 by the CVD method so as to fill trench 507b, through hole 507a, and opening 507c. Then, the entire surface of polycrystalline silicon film 517 is subjected to etching.
Referring to FIG. 61, filling layer 517a filling trench 507b is formed by etching with the upper surface thereof located within through hole 507a. Silicon oxide film 505 serves as an etching stopper during etching of polycrystalline silicon film 517. Silicon oxide film 505 is then removed.
Referring to FIG. 6.2, the surface of silicon nitride film 503 is exposed after removal of silicon oxide film 505.
Referring to FIG. 63, a silicon oxide film 519 is formed on filling layer 517a by thermal oxidation with silicon nitride film 503 maintained. Filling of through hole 507a is mostly completed by formation of silicon oxide film 519. During thermal oxidation processing at the time of formation of silicon oxide film 519, silicon nitride film 503 prevents entry of oxidation species into the silicon substrate for avoiding excess oxidation of the silicon substrate. Then, silicon nitride film 503 is removed by etching as shown in FIG. 64.
Advantages of the above described element isolation structure wherein element isolation oxide film 501b and trench 507b are combined are that the operation of the bipolar transistor can be kept at a high speed and that occurrence of a junction leak current can be prevented. The below description will be made on such advantages.
In the element isolation structure formed by combining element isolation oxide film 501b with trench 507b, channel stopper region 515 is formed in the region under trench 507b, and at the same time, channel stopper region 515 is formed in p.sup.- silicon substrate 521. Thus, the pn junction will not be formed between p.sup.+ channel stopper region 515 and a substrate. This also prevents generation of the parasitic capacitance by virtue of p.sup.+ channel stopper region 515, so that the high speed operation of the bipolar transistor can be maintained.
Further, p.sup.+ channel stopper region 515 is formed in the region under trench 507b, so as to secure a large distance between p.sup.+ channel stopper region 515 and an element (e.g., the bipolar transistor) formed on the surface of the substrate. In this regard, even if the pn junction is formed between p.sup.+ channel stopper region 515 and the substrate to generate the parasitic capacitance, influence of such parasitic capacitance on the elements formed on the surface of the substrate can be diminished. This improves the electrical isolation effect between respective elements and keeps the high speed operation of the bipolar transistor.
In the meantime, there are problems in the conventional element isolation structure, apart from the above described advantages.
In the conventional method of manufacturing the semiconductor device, as shown in FIG. 55, silicon nitride film 503 and silicon oxide film 505 are formed stacked successively after formation of element isolation oxide film 501b. Silicon oxide film 505 serves as the etching stopper during etching back of polycrystalline silicon film 517 in the step, shown in FIGS. 60 and 61. Silicon nitride film 503 prevents the entry of oxidation species into the lower layers, such as n.sup.- epitaxial growth layer 525 during thermal oxidation at the time of formation of silicon oxide film 519, so as to prevent oxidation of the lower layers in the steps shown in FIGS. 62 and 63.
The surface roughness of the internal wall of trench 507b is removed in the steps shown in FIGS. 57 and 58 after formation of silicon nitride film 503 and silicon oxide film 505. In other words, silicon oxide film 511 is removed by wet etching only after silicon oxide film 511 is once formed in trench 507b.
Supposing the element isolation structure is formed without removing the roughness in trench 507b, electrons and the like would easily move in the direction of arrow B along the roughness of trench 507b, as shown in FIG. 65. If electrons and the like can move easily across the element isolation region between adjacent elements, the electrical isolation capability between elements will be decreased significantly. In this regard, it is necessary to remove the roughness in trench 507b in order to prevent the decrease of the electrical isolation capability between elements.
Since, however, wet etching of silicon oxide film 511 shown in FIGS. 57 and 58 is carried out isotropically, element isolation oxide film 501b exposed from through hole 507a is simultaneously removed to a certain extent.
Referring to FIG. 58, a diameter W.sub.A of through hole 507a becomes wider than a diameter W.sub.B of silicon nitride film 503 due to isotropic etching of element isolation oxide film 501b. With this geometry, polycrystalline silicon layer 517 is formed by the CVD method or the like so as to fill trench 507b to obtain a sectional view shown in FIG. 66.
More specifically with reference to FIG. 66, polycrystalline silicon film 517 is formed on the entire surface to have an approximately uniform thickness by the CVD method. In other words, polycrystalline silicon film 517 is formed to reflect the stepped structure of the sidewalls of element isolation oxide film 501b and silicon nitride film 503. As a result, opening 507c is filled up before through hole 507a is completely filled, thus generating a void 517b in through hole 507a. Polycrystalline silicon film 517 is then etched back with void 517b generated to obtain a sectional view shown in FIG. 67.
Referring to FIG. 67, such a void leads to generation of a concave portion 517c in the upper surface of filling layer 517a formed by etching of polycrystalline silicon film 517. Accordingly, if oxide film 519 is formed on filling layer 517a, another concave portion 519c is generated on the surface of silicon oxide film 519 as shown in FIG. 68.
When patterning the conductive layer on the substrate with concave portion 519c on silicon oxide film 519, residue of the conductive layer will be generated in concave portion 519c.
FIG. 69 is a schematic sectional view showing the residue generated in such a concave portion, the view corresponding to the regions including the bipolar region and element isolation region shown in FIG. 51. FIG. 70 is a schematic plan view viewed from the direction of arrow C in FIG. 69. A sectional view taken along line A--A in FIG. 70 corresponds to FIG. 69.
With reference to FIGS. 69 and 70, in order to form, for example, conductive layer 535 for extracting the base electrode, the conductive layer is formed on the entire surface of the substrate, and then anisotropically etched for patterning. In the anisotropic etching, the residue is easily generated on the stepped sidewalls. Thus, a residue 535r of conductive layer 535 is generated along concave portion 519c.
In this case, the adjacent conductive layers are short-circuited because of residue 535r. More specifically, conductive layers 535a and 535b for extracting base electrode in the bipolar transistor, which are adjacent across the element isolation region, are short-circuited.
Therefore, in the conventional element isolation structure of the semiconductor device, respective conductive layers are short-circuited due to the residue left within concave portions.